Track 3 - Architectures and Accelerators

CHAIRS

  • Marco Danelutto, University of Pisa, Italy 
  • Ivy Peng, KTH Royal Institute of Technology, Sweden

Program Committee

TBA

FOCUS

  • Architectures for instruction-level and thread-level parallelism
  • Manycores, multicores, accelerators, domain-specific and special-purpose architectures, reconfigurable architectures
  • Cloud and HPC storage architectures and systems
  • Memory technologies and hierarchies
  • Exascale system designs; data center and warehouse-scale architectures
  • Novel big data architectures
  • Parallel I/O and storage systems
  • Power-efficient and green computing systems
  • Resilience, security, and dependable architectures
  • Software architectures spanning Edge, Cloud, HPC, and the computing continuum
  • Processing in memory and near-memory processing
  • Interconnect/memory architectures
  • Post-Moore systems: neuromorphic, quantum, hybrid